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FSDM311
Features
Green Mode Fairchild Power Switch (FPSTM)
* Internal Avalanche Rugged Sense FET * Precision Fixed Operating Frequency (67KHz) * Consumes Under 0.2W at 265VAC & No Load with Advanced Burst-Mode Operation * Internal Start-up Circuit * Pulse-by-Pulse Current Limiting * Over Voltage Protection (OVP) * Over Load Protection (OLP) * Internal Thermal Shutdown Function (TSD) * Auto-Restart Mode * Under Voltage Lockout (UVLO) with Hysteresis * Built-in Soft Start * Secondary Side Regulation
OUTPUT POWER TABLE
PRODUCT FSDM311 FSDM311L Open Frame(1) 230VAC15%(2) 13W 13W 85-265VAC 8W 8W
Notes: 1. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50C ambient. 2. 230 VAC or 100/115 VAC with doubler.
Applications
* Charger & Adapter for Mobile Phone, PDA & MP3 * Auxiliary Power for White Goods, PC, C-TV & Monitor
Typical Circuit
Related Application Notes
* AN-4137, 4141, 4147(Flyback) / AN-4134(Forward) / AN-4138(Charger)
AC IN
DC OUT
Vstr PWM
Drain
Description
The FSDM311 consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combines an VDMOS Sense FET with a voltage mode PWM control block. The integrated PWM controller features include: a fixed oscillator, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDM311 device reduces total component count, design size, weight while increasing efficiency, productivity and system reliability. This device provides a basic platform that is well suited for the design of cost-effective flyback converters.
Vfb
Vcc
Source
Figure 1. Typical Flyback Application
FPSTM is a trademark of Fairchild Semiconductor Corporation. (c)2005 Fairchild Semiconductor Corporation
Rev.1.0.9
FSDM311
Internal Block Diagram
Vstr 5 Vcc 2
UVLO Voltage Ref Internal Bias 9/7V
IDELAY 5uA IFB 400uA
L H
6,7,8
Drain
Vck OSC PWM DRIVER S R S/S 15mS
BURST
SFET
Vfb 3
Q
V BURL/ V BURH
LEB OLP
NC 4
Reset VSD Min.20V OVP
ILIM S R
TSD
Rsense Vth
Q
A/R
1
GND
Figure 2. Functional Block Diagram of FSDM311
2
FSDM311
Pin Definitions
Pin Number 1 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (9V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. The feedback voltage pin is the inverting input to the PWM comparator with its normal input level lies between 0.5V and 2.5V. It has a 0.4mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 4.5V triggers over load protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 4.5V using an internal 5uA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the Vcc reaches 9V, the internal switch is opened. The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer will decrease leakage inductance.
2
Vcc
3
Vfb
5
Vstr
6, 7, 8
Drain
Pin Configuration
8DIP 8LSOP GND 1 Vcc 2 Vfb 3 NC 4 8 Drain 7 Drain 6 Drain 5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDM311
Absolute Maximum Ratings
(Ta=25C, unless otherwise specified) Characteristic Drain Pin Voltage Vstr Pin Voltage Drain-Gate Voltage Gate-Source Voltage Drain Current Pulsed(1) Continuous Drain Current (Tc=25) Continuous Drain Current (Tc=100) Single Pulsed Avalanche Energy Supply Voltage Feedback Voltage Range Total Power Dissipation Operating Junction Temperature Operating Ambient Temperature Storage Temperature
(2)
Symbol VDRAIN VSTR VDG VGS IDM ID ID EAS VCC VFB PD TJ TA TSTG
Value 650 650 650 20 1.5 0.5 0.32 10 20 -0.3 to VSTOP 1.40 Internally limited -25 to +85 -55 to +150
Unit V V V V A A A mJ V V W C C C
Note: 1. Repetitive rating: Pulse width is limited by maximum junction temperature 2. L = 24mH, starting Tj = 25C
Thermal Impedance
(Ta=25C, unless otherwise specified) Parameter 8DIP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal(2) Symbol Value 88.84 13.94 Unit C/W C/W
JA JC
Note: 1. Free standing with no heatsink; Without copper clad. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. - all items are tested with the standards JESD 51-2 and 51-10 (DIP).
4
FSDM311
Electrical Characteristics
(Ta = 25C unless otherwise specified) Parameter SENSE FET SECTION Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance(1) Forward Trans-Conductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain (Miller) Charge CONTROL SECTION Switching Frequency Switching Frequency Variation(2) Maximum Duty Cycle UVLO Threshold Voltage Feedback Source Current Internal Soft Start Time Reference Voltage
(3)
Symbol
Condition VDS=650V, VGS=0V
VDS=520V, VGS=0V, TC=125C
Min. 1.0 61
Typ. 14 1.3 162 18 3.8 9.5 19 33 42 7.0 3.1 0.4 67 5 67 9 7 0.40 15 4.5 0.3 0.7 0.55 150 0.55 145 4.5 5 1.5 550
Max. 25 200 19 73 10 74 10 8 0.45 20 4.8 0.6 0.8 0.65 0.625 5.0 6 3.0 650
Unit
IDSS RDS(ON) gfs CISS COSS CRSS td(on) tr td(off) tf Qg Qgs Qgd fOSC fOSC DMAX VSTART VSTOP IFB tS/S VREF VREF/T VBURH
A S pF
VGS=10V, ID=0.5A VDS=50V, ID=0.5A VGS=0V, VDS=25V, f=1MHz
VDS=325V, ID=1.0A
ns
VGS=10V, ID=1.0A, VDS=325V
nC
KHz % % V V mA ms V mV/C V V mV A C V V A mA A
-25C Ta 85C VFB=GND VFB=GND 0V VFB 3V
60 8 6 0.35 10 4.2
Reference Voltage Varaiation with Temperature(2)(3) BURST MODE SECTION Burst Mode Voltage PROTECTION SECTION Peak Current Limit Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current
-25C Ta 85C
0.6 0.45 0.475 125 4.0 20
VBURL
Tj=25C
VBUR(HYS) Hysteresis ILIM TSD VSD VOVP IDELAY IOP ICH 3V VFB VSD VCC 16V VCC=0V , VSTR=50V
4 450
Note: 1. Pulse test: Pulse width 300us, duty 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production
5
FSDM311
Comparison Between FSDH0165 and FSDM311
Function Soft-Start FSDH0165 not applicable FSDM311 15ms FSDM311 Advantages * Gradually increasing current limit during soft-start further reduces peak current and voltage stresses * Eliminates external components used for soft-start in most applications * Reduces or eliminates output overshoot * Improves light load efficiency * Reduces power consumption at noload * Transformer audible noise reduction * Greater immunity to arcing provoked by dust, debris and other contaminants
Burst Mode Operation
not applicable
Built into controller
Drain Creepage at Package
1.02mm
3.56mm DIP 3.56mm LSOP
6
FSDM311
Typical Performance Characteristics (Control Part)
(These characteristic graphs are normalized at Ta = 25C)
1.15
1.15
1.10
1.10
1.05
1.05
Vref
0.95
Iop
-50 0 50 100 150
1.00
1.00
0.95
0.90
0.90
0.85
0.85
-50
0
50
100
150
Temperature('C)
Temperature('C)
Reference Voltage (VREF) vs. Ta
Operating Supply Current (IOP) vs. Ta
1.15
1.15
1.10
1.10
1.05
1.05
Vstart
Vstop
1.00
1.00
0.95
0.95
0.90
0.90
0.85
-50
0
50
100
150
0.85
-50
0
50
100
150
Temperature('C)
Temperature('C)
Start Threshold Voltage (VSTART) vs. Ta
Stop Threshold Voltage (VSTOP) vs. Ta
1.15
1.15
1.10
1.10
1.05
1.05
1.00
Dmax
-50 0 50 100 150
Fosc
1.00
0.95
0.95
0.90
0.90
0.85
0.85
-50
0
50
100
150
Temperature('C)
Temperature('C)
Operating Frequency (FOSC) vs. Ta
Maximum Duty Cycle (DMAX) vs. Ta
7
FSDM311
Typical Performance Characteristics (Continued)
1.15 1.15
1.15
1.10 1.10
1.10
1.05 1.05
1.05
Iover ILIM
0.95 0.95
Ifb
-50 -50 0 0 50 50 100 100 150 150
1.00 1.00
1.00
0.95
0.90 0.90
0.90
0.85 0.85
0.85
-50
0
50
100
150
Temperature('C) Temperature('C)
Temperature('C)
Peak Current Limit (ILIM) vs. Ta
Feedback Source Current (IFB) vs. Ta
1.15
1.15
1.10
1.10
1.05
1.05
Idelay
Vsd
1.00
1.00
0.95
0.95
0.90
0.90
0.85
-50
0
50
100
150
0.85
-50
0
50
100
150
Temperature('C)
Temperature('C)
Shutdown Delay Current (IDELAY) vs. Ta
Shutdown Feedback Voltage (VSD) vs. Ta
1.15
1.10
1.05
Vovp
1.00
0.95
0.90
0.85
-50
0
50
100
150
Temperature('C)
Over Voltage Protection (VOVP) vs. Ta
8
FSDM311
Functional Description
1. Startup : At startup, the internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in Figure 4. In the case of the FSDM311, when Vcc reaches 9V the device starts switching and the internal high voltage current source is disabled. The device is in normal operation provided that Vcc does not drop below 7V. After startup the bias is supplied from the auxiliary transformer winding.
Vin,dc ISTR IVcc = ISTR-ISTART IVcc = ISTR-ISTART Vstr J-FET ISTART
Vcc
UVLO Vref
FSDM311
Vin,dc ISTR Vstr Vcc
L
Vcc
VSTART
H
UVLO
Vcc must not drop below VSTOP
9V/ 7V
FSDM311
VSTOP Bias winding voltage t
Figure 4. Internal Startup Circuit
Figure 5. Charging Vcc Capacitor through Vstr
Calculating the Vcc capacitor is an important step to design with the FSDM311. At initial start-up in the FSDM311, the maximum value of start operating current ISTART is about 100uA, which supplies current to UVLO and Vref Blocks. The charging current IVcc of the Vcc capacitor is equal to Istr - 100uA. After Vcc reaches the UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At this time Vcc oscillates. In order to prevent this oscillation it is recommended that the Vcc capacitor be chosen to have the value between 10uF and 47uF.
2. Feedback Control : The FSDM311 is the voltage mode controlled device as shown in Figure 6. Usually, an optocoupler and KA431 type voltage reference are used to implement the feedback network. The feedback voltage is compared with an internally generated sawtooth waveform. This directly controls the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases, the feedback voltage Vfb is pulled down and it reduces the duty cycle. This will happen when the input voltage increases or the output load decreases.
Vcc 5uA
Vref 0.40mA
OSC
Vo
Vfb
Cfb
4 + VFB R
Gate driver
KA431
-
VSD
OLP
Figure 6. PWM and Feedback Circuit
9
FSDM311
3. Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the Sense FET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on. 4. Protection Circuit : The FSDM311 has several protective functions such as over load protection (OLP), over voltage protection (OVP), under voltage lock out (UVLO) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage V STOP (7V), the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage VSTART (9V), the device resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated.
4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. In order to avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. In conjunction with the Ipk current limit pin (if used) the current mode feedback path would limit the current in the Sense FET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (Vo) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5uA current source (IDELAY) starts to charge Cfb slowly up to Vcc. In this condition, VFB increases until it reaches 4.5V, when the switching operation is terminated as shown in Figure 8. The shutdown delay time is the time required to charge Cfb from 3V to 4.5V with 5uA current source.
VFB Over Load Protection 4.5V
OSC
3V
5uA 400uA
Vfb
4 R
+ OLP
S R
Q
GATE DRIVER
t12= CFBx(V(t2)-V(t1)) / IDELAY
S Q
Cfb
RESET
4.5V
TSD
R A/R
FSDM311 OLP, TSD Protection Block
t1
t12 = C FB V ( t 2 ) - V ( t1 ) ; I DELAY
t2
t
I DELAY = 5 A , V ( t1 ) = 3V , V ( t 2 ) = 4 . 5V
Figure 7. Protection Block
Figure 8. Over Load Protection (OLP)
4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to detect the temperature of the Sense FET. When the temperature exceeds approximately 145C, thermal shutdown is activated.
10
FSDM311
5. Soft Start : The FPS has an internal soft start circuit that slowly increases the feedback voltage together with the Sense FET current after it starts up. The typical soft start time is 15msec, as shown in Figure 9, where progressive increments of the Sense FET current are allowed during the start-up phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode.
Vo
Vo set
V FB
0.7V 0.55V
Ids
Vds
D rain curre n t 0 .5 5 A 2 .1 4 m s 7 ste p s
t
0 .3 1 A
OSC
S Q
t
Vfb
4
5uA
400uA
GATE DRIVER
on/off
R
Figure 9. Internal Soft Start
0.70V /0.55V
FSDM311 Burst Operation Block
Figure 10. Burst Operation Function
6. Burst operation : In order to minimize the power dissipation in standby mode, the FSDM311 enters burst mode operation. As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below VBURL(0.55V). At this point switching stops and the output voltages start to drop. This causes the feedback voltage to rise. Once is passes VBURH(0.70V) switching starts again. The feedback voltage falls and the process repeats. Burst mode operation alternately enables and disables switching of the power MOSFET to reduce the switching loss in the standby mode.
11
FSDM311
Application Tips
1. Methods of Reducing Audible Noise Switching mode power converters have electronic and magnetic components, which generate audible noises when the operating frequency is in the range of 20~20,000 Hz. Even though they operate above 20 kHz, they can make noise depending on the load condition. Designers can employ several methods to reduce these noises. Here are three of these methods: Glue or Varnish The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise. But, it also can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio according to the temperature. Ceramic Capacitor Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise reduction solution. Some dielectric materials show a piezoelectric effect depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is considerable to use a zener clamp circuit instead of an RCD snubber for higher efficiency as well as lower audible noise. Adjusting Sound Frequency Moving the fundamental frequency of noise out of 2~4 kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4 kHz. When the fundamental frequency of noise is located in this range, one perceives the noise as louder although the noise intensity level is identical. Refer to Figure 11. Equal Loudness Curves. When FPS acts in Burst mode and the Burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of Burst mode operation lies in the range of 2~4 kHz, adjusting feedback loop can shift the Burst operation frequency. In order to reduce the Burst operation frequency, increase a feedback gain capacitor (CF), opto-coupler supply resistor (RD) and feedback capacitor (CB) and decrease a feedback gain resistor (RF) as shown in Figure 12. Typical Feedback Network of FPS.
Figure 11. Equal Loudness Curves
Figure 12. Typical Feedback Network of FPS
2. Other Reference Materials AN-4134: Design Guidelines for Off-line Forward Converters Using Fairchild Power Switch (FPSTM) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS) AN-4138: Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPSTM) AN-4140: Transformer Design Consideration for Off-line Flyback Converters using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147: Design Guidelines for RCD Snubber of Flyback AN-4148: Audible Noise Reduction Techniques for FPS Applications
12
FSDM311
Package Dimensions
8DIP
13
FSDM311
Package Dimensions (Continued)
8LSOP
14
FSDM311
Ordering Information
Product Number FSDM311 FSDM311L Package 8DIP 8LSOP Marking Code DM311 DM311 BVDSS 650V 650V fOSC 67KHz 67KHz RDS(ON) 14 14
15
FSDM311
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 9/29/05 0.0m 001 (c) 2005 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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